1. Field of the Invention
The present invention relates to a semiconductor memory device and a data processing system including the same, and, more particularly relates to a semiconductor memory device to which an address signal is input in a plurality of steps, and a data processing system including the same.
2. Description of Related Art
DRAM (Dynamic Random Access Memory), which is one of representative semiconductor memory devices, has a very large address space, and thus an address multiplex system in which an address signal is input in two steps is used. In this system, the number of address buses or of address terminals can be reduced.
Specifically, in synchronism with an active command, a block address (a mat address) and a row address are provided. Subsequently, in synchronism with a read command or a write command, a column address is provided. In this way, a memory cell to be accessed is specified. As a result, by the block address and the row address that are firstly provided, a memory cell array (also called a mat or a block) and a word line included in a selected memory cell array are selected, and by the column address that is secondly provided, a bit line is selected.
Such an address input system is predetermined depending on each specification. Therefore, in order that semiconductor memory devices other than the DRAM have a compatibility with a DRAM, it becomes essential for those semiconductor memory devices to adopt the above address input system. However, a semiconductor memory device in which the speed of a read operation or a write operation is slower than that of DRAMs, for example, a semiconductor memory device such as a PRAM (Phase Change Random Access Memory) in which a phase change material is used for a memory cell, has a problem in that it is not possible to automatically satisfy other specifications for DRAMs (particularly, an access cycle), and, even when the address input system is matched, it is not sufficient to secure a compatibility.
As a method of solving such a problem, Japanese Patent Application Laid-open No. 2005-158199 proposes a method in which a set operation (an operation in which a phase change material is changed from a highly resistant amorphous state to a low resistant crystalline state) of a memory cell that particularly requires a time is performed in the background.
However, there is a problem in that, to realize the method according to Japanese Patent Application Laid-open No. 2005-158199, there is a need of arranging a write amplifier for each bit line, and inevitably the area occupied by the write amplifiers on a chip becomes very large. That is, in a write operation in a PRAM, there is a need of applying a high voltage to the bit line and also supplying a relatively large writing current, and thus each of the write amplifiers occupies a very large area unlike a sense amplifier in the DRAM. Thus, it is not realistic to arrange the write amplifier for each bit line.
Such a problem occurs not only in PRAMs, but also in other semiconductor memory devices in which its write operation requires a long time.